#ifndef _TIM_HW_H_
#define _TIM_HW_H_

#include "soc.h"

typedef struct {
	_RW CR1;         /*!< TIM control register 1,              offset: 0x00 */
	_RW CR2;         /*!< TIM control register 2,              offset: 0x04 */
	_RW RESERVED0[1];
	_RW DIER;        /*!< TIM DMA/interrupt enable register,   offset: 0x0C */
	_RW SR;          /*!< TIM status register,                 offset: 0x10 */
	_RW EGR;         /*!< TIM event generation register,       offset: 0x14 */
	_RW RESERVED1[3];
	_RW CNT;         /*!< TIM counter register,                offset: 0x24 */
	_RW PSC;         /*!< TIM prescaler,                       offset: 0x28 */
	_RW ARR;         /*!< TIM auto-reload register,            offset: 0x2C */
} TIM_BaseStruct;

extern TIM_BaseStruct SOC_TIM6;
extern TIM_BaseStruct SOC_TIM7;

/**
 * 使能、更新事件、单脉冲、影子模式
 */
#define TIM_BASE_CR1_DIS          (0x0U<<0)  /* 停止计数 */
#define TIM_BASE_CR1_EN           (0x1U<<0)  /* 单脉冲模式下，硬件自动清零，
                                                触发模式下可由硬件置一 */
#define TIM_BASE_CR1_UEV_NONE     (0x1U<<1)  /* 忽略更新事件，各影子寄存器的
                                                数值保持不变，UG标志仍可以重
                                                新初始化计数器 */
#define TIM_BASE_CR1_UEV_OVER     (0x2U<<1)  /* 仅响应计数器上/下溢 */
#define TIM_BASE_CR1_UEV_ALL      (0x0U<<1)  /* 计数器上/下溢、UG位置1、从模式
                                                更新等事件 */
#define TIM_BASE_CR1_OPM_DIS      (0x0U<<3)
#define TIM_BASE_CR1_OPM_EN       (0x1U<<3)  /* 启用单脉冲模式 */
#define TIM_BASE_CR1_ARPE_DIS     (0x0U<<7)
#define TIM_BASE_CR1_ARPE_EN      (0x1U<<7)  /* 启用影子寄存器 */

/**
 * 主从模式，配置TRGO信号的触发源
 */
#define TIM_BASE_CR2_MMS_UG       (0x0U<<4)  /* 使用UG信号触发 */
#define TIM_BASE_CR2_MMS_EN       (0x1U<<4)  /* 使用使能信号触发 */
#define TIM_BASE_CR2_MMS_UEV      (0x2U<<4)  /* 使用事件更新信号触发 */

/**
 * 中断/DMA触发
 */
#define TIM_BASE_DIER_UIE_DIS     (0x0U<<0)
#define TIM_BASE_DIER_UIE_EN      (0x1U<<0)  /* 使能更新中断 */
#define TIM_BASE_DIER_UDE_DIS     (0x0U<<0)
#define TIM_BASE_DIER_UDE_EN      (0x1U<<0)  /* 使能DMA请求 */

/**
 * 状态，写零清除
 */
#define _TIM_BASE_IsInterrupt(dev)    ((dev).SR)
#define _TIM_BASE_ClearInterrupt(dev) ((dev).SR = 0x0U)

/**
 * 事件生成，硬件自清零，重新初始化计数器，所有计数值，包括预分频的计数值清零，
 * 产生更新事件。第一次初始定时器时需要执行一下该动作，否则第一个周期有点问题，
 * 暂不清楚是为什么。单脉冲模式下，UG事件会终止当前脉冲，停止计数
 */
#define TIM_BASE_EGR_UG_EN        (0x1U<<0)

/**
 * 当前计数值，递增计数，十六位
 */
#define _TIM_BASE_GetCounter(dev) ((dev).CNT)

/**
 * 预分频
 */
#define TIM_BASE_PSC_1_65536D(val) ((val)-1)

/**
 * 自动重装计数器
 */
#define TIM_BASE_ARR_1_65536D(val) ((val)-1)  /* 为1时，计数器不工作 */

#if 0
typedef struct {
	_RW CR1;         /*!< TIM control register 1,              offset: 0x00 */
	_RW CR2;         /*!< TIM control register 2,              offset: 0x04 */
	_RW SMCR;        /*!< TIM slave mode control register,     offset: 0x08 */
	_RW DIER;        /*!< TIM DMA/interrupt enable register,   offset: 0x0C */
	_RW SR;          /*!< TIM status register,                 offset: 0x10 */
	_RW EGR;         /*!< TIM event generation register,       offset: 0x14 */
	_RW CCMR1;       /*!< TIM capture/compare mode register 1, offset: 0x18 */
	_RW CCMR2;       /*!< TIM capture/compare mode register 2, offset: 0x1C */
	_RW CCER;        /*!< TIM capture/compare enable register, offset: 0x20 */
	_RW CNT;         /*!< TIM counter register,                offset: 0x24 */
	_RW PSC;         /*!< TIM prescaler,                       offset: 0x28 */
	_RW ARR;         /*!< TIM auto-reload register,            offset: 0x2C */
	_RW RCR;         /*!< TIM repetition counter register,     offset: 0x30 */
	_RW CCR1;        /*!< TIM capture/compare register 1,      offset: 0x34 */
	_RW CCR2;        /*!< TIM capture/compare register 2,      offset: 0x38 */
	_RW CCR3;        /*!< TIM capture/compare register 3,      offset: 0x3C */
	_RW CCR4;        /*!< TIM capture/compare register 4,      offset: 0x40 */
	_RW BDTR;        /*!< TIM break and dead-time register,    offset: 0x44 */
	_RW DCR;         /*!< TIM DMA control register,            offset: 0x48 */
	_RW DMAR;        /*!< TIM DMA address for full transfer,   offset: 0x4C */
	_RW OR;          /*!< TIM option register,                 offset: 0x50 */
} TIM_BaseStruct;


typedef struct {
	_RW CR1;         /*!< TIM control register 1,              offset: 0x00 */
	_RW CR2;         /*!< TIM control register 2,              offset: 0x04 */
	_RW SMCR;        /*!< TIM slave mode control register,     offset: 0x08 */
	_RW DIER;        /*!< TIM DMA/interrupt enable register,   offset: 0x0C */
	_RW SR;          /*!< TIM status register,                 offset: 0x10 */
	_RW EGR;         /*!< TIM event generation register,       offset: 0x14 */
	_RW CCMR1;       /*!< TIM capture/compare mode register 1, offset: 0x18 */
	_RW CCMR2;       /*!< TIM capture/compare mode register 2, offset: 0x1C */
	_RW CCER;        /*!< TIM capture/compare enable register, offset: 0x20 */
	_RW CNT;         /*!< TIM counter register,                offset: 0x24 */
	_RW PSC;         /*!< TIM prescaler,                       offset: 0x28 */
	_RW ARR;         /*!< TIM auto-reload register,            offset: 0x2C */
	_RW RCR;         /*!< TIM repetition counter register,     offset: 0x30 */
	_RW CCR1;        /*!< TIM capture/compare register 1,      offset: 0x34 */
	_RW CCR2;        /*!< TIM capture/compare register 2,      offset: 0x38 */
	_RW CCR3;        /*!< TIM capture/compare register 3,      offset: 0x3C */
	_RW CCR4;        /*!< TIM capture/compare register 4,      offset: 0x40 */
	_RW BDTR;        /*!< TIM break and dead-time register,    offset: 0x44 */
	_RW DCR;         /*!< TIM DMA control register,            offset: 0x48 */
	_RW DMAR;        /*!< TIM DMA address for full transfer,   offset: 0x4C */
	_RW OR;          /*!< TIM option register,                 offset: 0x50 */
} TIM_BaseStruct;
#endif

#endif /* _TIM_HW_H_ */
